Craig Zilles
  Associate Professor of Computer Science
short biography

Research Interests
  computer architecture, compiler construction, dynamic optimization, and computer science/engineering education.

Research Projects
  • Hardware/Software Co-designed Run-times for Managed and Dynamic Languages
  • Transactional Memory
  • Efficient Microarchitectures
  • Concept Inventories for Computer Science (CS Education)
  • Master/Slave Speculative Parallelization
  • Selected recent publications
  • Characterizing and Optimizing the Memory Footprint of De Novo Short Read DNA Sequence Assembly (ISPASS 2009)
  • BlueShift: Designing Processors for Timing Speculation from the Ground Up (HPCA 2009)
  • Proof by Incomplete Enumeration and Other Logical Misconceptions (ICER 2008)
  • FeS2 (Full-system Execution-driven Simulator for x86) released
  • Using Hardware Memory Protection to Build a High-Performance, Strongly Atomic Hybrid Transactional Memory (ISCA 2008)
  • A Characterization of Instruction-Level Error Derating and its Implications for Error Detection (DSN/PDS 2008)
  • An Analysis of I/O And Syscalls In Critical Sections And Their Implications for Transactional Memory (ISPASS 2008)
  • Branch-on-Random (CGO 2008)
  • Accurate Critical Path Analysis via Random Trace Construction (CGO 2008)
  • Fundamental Performance Challenges in Horizontal Fusion of In-Order Cores (HPCA 2008)
  • Identifying Important and Difficult Concepts in Introductory Computing Courses using a Delphi Process (SIGCSE 2008) extended version
  • "Hardware Atomicity for Reliable Software Speculation" has been selected for IEEE Micro Top Picks (2008)
  • Accordion Arrays: Selective Compression of Unicode Arrays in Java (ISMM 2007)
  • Implications of False Conflict Rate Trends for Robust Software Transactional Memory (IISWC 2007)
  • An Analysis of I/O and Syscalls in Critical Sections and Their Implications for Transactional Memory (Transact 2007)
  • Delta Execution for Software Reliability (HotDep 2007)
  • Dependence-based Scheduling Revisited: A Tale of Two Baselines (WDDD 2007)
  • Hardware Atomicity for Reliable Software Speculation (ISCA 2007)
  • Transactional Memory and the Birthday Paradox (SPAA 2007)
  • Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions (Transact 2006)
  • Probabilistic Counter Updates for Predictor Hysteresis and Stratification (HPCA 2006)
  • A Criticality Analysis of Clustering in Superscalar Processors (Micro 2005)
  • Challenges to Providing Performance Isolation in Transactional Memories (WDDD 2005)
  • Formally Defining and Verifying Master/Slave Speculative Parallelization (FM`05)
  • Reactive Techniques for Controlling Software Speculation (CGO 2005)
  • SPIMbot: An Engaging, Problem-based Approach to Teaching Assembly Language Programming (SIGCSE 2005) presentation software
  • Targeted Path Profiling (CGO-2) presentation
  • Master/Slave Speculative Parallelization (Micro-35) presentation
  • Execution-based Prediction Using Speculative Slices (ISCA-2001)
  • Benchmark Health Considered Harmful (CAN)

    Full list of publications

  • Teaching
  • CS232 - Computer Architecture II
  •   FA03, SP04, FA04, SP05, SP06, SP07, FA07, SP08
  • CS497/CS598cz - Dynamic Translation and Optimization
  •   FA02, SP03, FA05

    Graduate Students
  • Lee Baugh
  • Jeff Cook
  • Geoffrey Herman
  • Edward Lee
  • Naveen Neelakantam
  • Nicholas Riley
  • Charles Tucker
  • Changrui Yuan
  • Student Theses
      Principles of Instruction-Level Distributed Processing Pierre Salverda Ph.D. Thesis, April 2008.

      Efficient User-Mode Exception Handling in x86 Linux Chris Eben, B.S. Thesis, August 2007 (Microsoft)
      Boolean Blunders: Identification and Assessment of Student Misconceptions in a Digital Logic Course J.T. Longino, M.S. Thesis, July 2006 (AMD)
      Profile-directed If-Conversion in Superscalar Microprocessors Eric Zimmerman, M.S. Thesis, July 2005 (Citadel Investment Group)
      Design of an MSSP Verify/Commit Unit Partheesh Mani, M.S. Thesis, August 2005 (Intel Corporation)
      Limited Path Profiling and Correlated Branch Elimination Andrew Nicholson, M.S. Thesis, April 2005 (
      TraceVis: An Execution Trace Visualization Tool James Roberts, M.S. Thesis, July 2004 (nVIDIA architecture group)
      A Task Optimization Framework for MSSP Rahul Ulhas Joshi, M.S. Thesis, May 2004 (nVIDIA compiler group)
      An Assembler for the MSSP Distiller Eric Zimmerman, B.S. Thesis, May 2004 (continuing for M.S.)
      Program Orienteering Naveen Neelakantam, M.S. Thesis, April 2004 (continuing for Ph.D.)

  • Advice for Undergraduates
  • Advice for Graduate Students

  • UIUC Computer Architecture:   Group   Seminar   Mailing List
    UIUC Compiler:   Group   Seminar   Mailing List


    Contact Information:

       Siebel Center 4112
       217-244-0553 (Phone)
       217-244-6621 (Assistant - Sheila Clark)
       217-265-6582 (Fax)

    Postal address:
       University of Illinois at Urbana-Champaign
       Department of Computer Science
       Siebel Center    MC-258
       201 N. Goodwin Ave.
       Urbana, IL 61801-2302